1. Field of the Invention
The present invention relates to a chip package, and in particular relates to a chip package formed by a wafer-level packaging process and manufacturing methods thereof.
2. Description of the Related Art
A chip package is used to protect a chip packaged therein and provides conducting routes between the chip and an external electronic element. In the present wafer level packaging process, the chip packages located in the periphery region of the wafer may suffer from problems such as bad adhesion and/or moisture infiltration, which largely affects the operation of the packaged chip.
Thus, it is desired to improve the reliability of chip packages.